The present invention relates to an image sensor, and more particularly to a CMOS active pixel sensor that is configured with a distributed operational amplifier architecture with only the differential input transistors placed inside the pixels, where the rest of the operational amplifier circuit is placed outside the pixel array, and the operational amplifier can be configured for unit gain to achieve high performance pixel readout with reduced transistor mismatch problem.
CMOS active pixel sensors (APS) are used in a wide range of imaging applications. A conventional CMOS APS is illustrated in the circuit diagram in FIG. 1. The APS includes a photodiode D1 (or other photo sensing elements) acting as light sensing means, which is coupled to the gate of a N-channel transistor M1. The transistor M1 is configured as a source follower amplifier which in turn drives the external circuit through a row select transistor M2, which connects M1 to the bit line, which in turn is connected to the external circuit. The photodiode D1 is also connected to a reset transistor M3, which resets the photodiode to an initial integration voltage of (VR−VT), wherein the VR is the reset voltage and the voltage VT is a threshold voltage of the reset transistor M3.
With reference to FIG. 2, operations of the APS are typically performed in cycles (or frame intervals) of three steps: (1) reset: the photodiode D1 in the APS is reset to the initial integration voltage; (2) image integration: the light energy is collected and converted into an electrical signal through the photodiode D1; (3) read out: at the end of the image integration period, the voltage Vd across the photodiode D1 is equal to (VR−VT−Vs), wherein the voltage Vs is a voltage change due the photons absorbed in the photodiode D1.
Thus, voltage Vs corresponds to the absorbed photons and can be determined by subtracting the voltage at the end of the image integration period from the voltage at the beginning of the image integration period. That is, the voltage Vs is (VR−VT)−(VR−VT−VS). Following the image integration period, the APS is read out by turning on the row select transistor M2 (which has been kept off until this point in the cycle). When the voltage across the photodiode D1 decreases, the gate voltage of the source follower transistor M1 is reduced, causing a reduction in the amount of current flowing to the bit line through the row select transistor M3. Therefore, a voltage VP (referred as “pixel voltage”) on the bit line can be measured by a conventional current detector. A graphical illustration of the pixel voltage of the active pixel sensor is shown in FIG. 2.
One problem of the above described CMOS APS is the source follower gain variation of M1 from one APS to another due to variations of MOSFET thresholds. The source follower gain variation results in a pixel to pixel gain mismatch.
Another problem of the read out circuitry of the APS in FIG. 1 is associated with large format image sensors, where the APS are arranged to form a large array or matrix. FIG. 3 is a schematic diagram of an APS imaging system. The APS imaging system 300 has a row decoder 310, a plurality of APS output circuits 320 (such as correlative double sampling circuits), a timing controller 330, and an array of APS 340. Each APS 340 is capable of converting a detected quantity of light to corresponding electrical signal at the output circuits 320. A plurality of control lines 350 extend along corresponding sensor rows from the row decoder 310 and are connected to corresponding pixel sensors 340 in the respective sensor row. Each of the control lines 350 includes a select line 352 and a reset line 354. Each APS output in the corresponding sensor column is coupled by a column output line 360 such as a bit line. In operation, the timing controller 330 provides timing signals to the row decoder 310, which sequentially activates each row of active pixel sensors 340 via the control lines 350 to detect the light intensity and to generate the corresponding output voltage signals during each frame interval.
Each column may have a large number of sensors 340. The source follower M1 drives the entire column during read out and hence drives the entire bit line capacitance. The large driving load requires a more powerful source follower M1 and row select transistor M2. The more powerful M1 and M2, the larger the transistor size, and thus the higher total bus (bit line) capacitance. The higher bus capacitance makes the bus even harder to drive. Therefore, the evolution of the system eventually reaches a point of diminishing return.
To improve the performance of the APS and to allow the construction of large APS array for high resolution APS imaging system, an improved read out circuits is required. The main requirement for an improved read out circuit is gain accuracy. As widely known, the best approach for this is to use a high gain amplifier combined with an accurate feedback network. FIG. 4 is a schematic diagram of an APS connected to a high gain operational amplifier A1 configurated to have unit gain through negative feedback. The output of the operational amplifier A1 is connected to the bit line through a switch S1, which can be constructed by NMOS transistor. Since operational amplifier in negative feedback form is robust to process variation, therefore, the constructed APS imaging system will not suffer from pixel to pixel gain mismatch problem.
However, the limited amount of chip area is the prime constraint in implementing the APS imaging system. High density, mega pixel imaging systems require compact image sensing elements and thus leave very little room for circuitry. Therefore, it is undesirable to put the complete operational amplifier structure within the pixel, as the resulting increase in sensor area would make the sensor too expensive.
Distributed amplifiers have been used to address the afore-mentioned problem. A certain part of the operational amplifier circuit is implemented inside the pixel, while the rest is in the column circuitry, and is shared by all the pixels of a column. On way to include the operational amplifier within the pixel in a distributive way has been described in the U.S. Pat. No. 6,084,229, which is incorporated herein by reference. According to the disclosure of the patent (see FIG. 5), the APS 500 includes one of the differential input transistors M4 of the operational amplifier A2 is on-pixel and connected to the +bit line 510 and −bit line 520 through the row select transistor M6. In contrast, the other differential input transistor M5 and the associated circuitry of the operational amplifier are off pixel. There can be a plurality of input transistors M4, each at a respective pixel, all connected to the same operational amplifier A2.
However, there are a number of parasitic effects with such partitioning of the operational amplifier circuit between column and pixel. When the differential pair (M4 and M5) of the amplifier is divided between pixel and column, the mismatch between M4 and M5 will result in high output offset, low common mode rejection ratio, and low power supply rejection ratio. Furthermore, since the column lines will be long, there will be a lot of parasitic capacitance to be added to M4 and will thus further enhance the mismatch between the differential pair and further reduce the performance of the constructed operational amplifier A2, and hence the read out circuitry of the APS.
There is thus a need for improved distributed amplifiers for APS.